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Paper   IPM / Physic / 6891
School of Physics
  Title:   A High-Speed Low-Noise Transimpedance Amplifier in A 0.25 μm CMOS Technology
1.  G. Anelli
2.  K. Borer
3.  L. Casagrande
4.  M. Despeisse
5.  P. Jarron
6.  N. Pelloux
7.  S. Saramad
  Status:   Published
  Journal: Nucl. Instrum. Meth. A
  No.:  114
  Vol.:  512
  Year:  2003
  Pages:   117-128
  Supported by:  IPM
We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 k, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO2) without any degradation in the performance.

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