| | A paper by Dr. Seyed Mohammad Sadrosadati and his collaborators, titled Reducing DRAM Latency via Fine-grained In-DRAM Cache has been accepted for publication in MICRO 2020, a top-tier computer architecture conference.
To improve DRAM latency, in-DRAM cache has been proposed by introducing heterogeneity into DRAM banks, where one region has a normal access latency and capacity, while the other has a fast access latency but small capacity, serving as an inclusive in-DRAM cache. However, such design suffers from the inefficient data relocation operations between fast and normal regions, where 1) the relocation granularity is an entire DRAM row, leading to limited performance improvement due to low data locality, and 2) the relocation latency increases with the increase of the physical distance between fast and normal regions so that multiple fast regions are required and interleaved among normal regions to reduce data relocation latency, resulting in increased overhead and manufacturing complexity.
In this paper, the authors observe that the global row buffer in a DRAM bank is interconnected with all of the banks local row buffers. This enables building an efficient substrate, which can perform cache-block level data relocation within a DRAM bank at a distance independent latency. Based on this substrate, the authors propose a fine-grained (i.e., sub-DRAM-row) in-DRAM cache (FG-Cache). The corresponding benefits are three-fold: 1) increased performance improvement, as multiple hot sub-DRAM-rows can be combined into one single DRAM row of the in-DRAM cache, the overall performance is substantially increased due to a higher in-DRAM cache hit and row buffer hit rate; 2) simplified in-DRAM cache design, fewer fast regions are needed and no longer necessary to be interleaved among normal regions; 3) potential benefit for conventional homogeneous DRAM chip, considerable performance gains can be achieved even by simply reserving a few DRAM rows in conventional DRAM chips to collocate hot sub-DRAM-rows.
The evaluations across a wide variety of applications show that FG-Cache improves the average performance of a system using DDR4 DRAM by 16.3% and reduces average DRAM energy consumption by 7.8% for 8-core workloads. The authors show the performance gains are robust across many system and mechanism parameters. | |
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