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Paper   IPM / Cognitive Sciences / 17820
School of Cognitive Sciences
  Title:   A hardware efficient intra-cortical neural decoding approach based on spike train temporal information
  Author(s): 
1.  D. Katoozian
2.  H. Hosseini-Nejad
3.  MR. Abolghasemi Dehaqani
4.  A. Shoeibi
5.  J. Manuel Gorriz
  Status:   Published
  Journal: Integrated Computer-Aided Engineering
  No.:  4
  Vol.:  29
  Year:  2022
  Pages:   431-445
  Supported by:  IPM
  Abstract:
Motor intention decoding is one of the most challenging issues in brain machine interface (BMI). Despite several important studies on accurate algorithms, the decoding stage is still processed on a computer, which makes the solution impractical for implantable applications due to its size and power consumption. This study aimed to provide an appropriate real-time decoding approach for implantable BMIs by proposing an agile decoding algorithm with a new input model and implementing efficient hardware. This method, unlike common ones employed firing rate as input, used a new input space based on spike train temporal information. The proposed approach was evaluated based on a real dataset recorded from frontal eye field (FEF) of two male rhesus monkeys with eight possible angles as the output space and presented a decoding accuracy of 62%. Furthermore, a hardware architecture was designed as an application-specific integrated circuit (ASIC) chip for real-time neural decoding based on the proposed algorithm. The designed chip was implemented in the standard complementary metal-oxide-semiconductor (CMOS) 180 nm technology, occupied an area of 4.15 mm2, and consumed 28.58 μW @1.8 V power supply.

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