In nano-electronics, the overall reliability is determined by the temperature of the hottest zone on the die. Hence, the selection of materials and also the heat spreader design, as a thermal management solution for managing the temperature of the spots known as hotspots, are proposed. Beside the attempts to find the proper methods for heat removal, finding the low-dimensional silicon replacement candidates, with the lowest maximum temperature, is the most proper and perfect choice for the nano-electronics industry. Accordingly, the transistor with a lower maximum temperature can be easier kept under the threshold temperature. Consequently, it is necessary to study the thermal behavior of the electrically- efficient FETs, to make sure that they also present energy efficiency for better cooling and operation. In the present seminar, first, the developed formalism for investigation of thermal behavior in common 3-D silicon transistors is introduced. The non-Fourier thermal attitudes are studied using the non-equilibrium Monte-Carlo simulation of the phonon Boltzmann equation. Then, the formalism is used to study well-known two- dimensional replacements for silicon channels such as graphene, blue phosphorene, germanene, silicene, MoS2 and recently, the two-dimensional complex MA2Z4 structures. Specifically, two materials of MoSi2N4 and WSi2N4 due to their proper electrical and thermal characteristics are investigated. Our calculations establish that MoSi2N4 and WSi2N4 present lower peak temperature rise. In fact, the phonon analysis shows that the competition between the dominant heat carrier velocity, and its related frequency determines the maximum temperature value. Particularly, the material WSi2N4 with much more phonons in TA mode, with almost high velocity and relatively low-frequency, has adequate thermal condition, and its peak temperature is very low.


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